Levo - A Scalable Billion Transistor CPU
نویسندگان
چکیده
The Levo high ILP microarchitecture is described and evaluated. Levo employs instruction time-tags and active stations to ensure correct operation in a rampantly speculative and out-oforder resource flow execution model. The Tomasulo-algorithm-like broadcast buses are segmented; their lengths are constant, that is, do not increase with machine size. This helps to make Levo scalable. Known High-ILP techniques such as Disjoint Eager Execution and Minimal Control Dependencies are implemented in novel ways. Examples of basic Levo operation are given. A chip floorplan of Levo is presented, demonstrating feasibility and little cycle-time impact. Levo is simulated, characterizing its basic geometry and its performance.
منابع مشابه
Levo - A Scalable Processor With High IPC
UHT, MORANO, KHALAFI & KAELI 2 description of the microarchitecture, a description of the physical layout (a floorplan), and many new simulation results. The paper is organized as follows. In Section 2 we review major impediments to high IPC realization. Section 3 provides the Levo logical description, and discusses Levo’s solutions to the high IPC problems. Other implementation issues are addr...
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